Second, high power NTC thermal gold electrodes chip / silver electrode wafer packaging key technology.
Packaging high-power NTC thermal gold electrode and silver electrode wafers primarily involves considerations of light, heat, electricity, structure, and technology, illustrated in Figure 1 below. These factors are interdependent and mutually influential. Among them, light serves as the objective for encapsulating NTC thermal gold electrode and silver electrode chips, with heat being pivotal. Electricity, structure, and technology serve as the means to achieve encapsulation, and the performance reflects the level of encapsulation.
To streamline production processes and reduce costs, the design of NTC thermal gold electrode and silver electrode wafer packaging should be synchronized with chip design. This ensures that the encapsulation structure and processes are considered during chip design. Otherwise, adjustments to chip structure for encapsulation needs after chip manufacturing completion could prolong product development cycles and increase costs, and in some cases, be impractical.
Specifically, key technologies for encapsulating high-power NTC thermal gold electrode and silver electrode chips include:
- Low thermal resistance encapsulation technology is crucial for enhancing the efficiency of NTC thermal gold and silver electrode chips. These chips convert about 80% of their power input into heat due to their small surface area. Therefore, effective packaging is essential, involving chip layout, selection of packaging and substrate materials, thermal interface materials, and heat sink design.
- The thermal resistance of NTC thermal gold and silver electrode chip packaging includes material resistance (from the heat dissipation substrate and heat sink structure) and interface thermal resistance. The heat dissipation substrate’s role is to absorb heat from the chip and transfer it to the heat sink for dissipation into the surroundings. Common substrate materials include silicon, metals like aluminum and copper, ceramics such as AlN and SiC, and composite materials.
- Third-generation Nichia chips utilize CuW substrates to reduce thermal resistance and enhance semiconductor efficiency. Lamina Ceramics has developed low-temperature co-firing ceramic-to-metal substrates for high-power chips, enabling direct welding of NTC electrode chips to ceramic substrates. This approach improves thermal performance by reducing thermal interface resistance and simplifying the structure.
Another advancement by Curmilk involves high thermal conductivity copper ceramic boards, formed by sintering ceramic substrates (such as AlN) with a high-temperature, high-pressure process, eliminating the need for adhesives. These substrates offer excellent thermal conductivity, high strength, and strong insulation properties, making them suitable for high-power NTC electrode arrays.
Research indicates that the thermal resistance at the encapsulation interface significantly impacts cooling effectiveness. Poor handling of this interface can compromise cooling efficiency. For instance, interfaces that maintain good contact at room temperature may separate at high temperatures, leading to substrate warping and affecting bonding and local heat dissipation. Improving the packaging of NTC thermal gold and silver electrode wafers involves minimizing interface contact resistance and enhancing heat dissipation. Therefore, careful selection of materials for the chip-to-substrate thermal interface (TIM) is crucial.
NTC thermal gold and silver electrode wafer packaging typically employs TIM such as conductive adhesives and thermal conductivity glues, which have low thermal conductivity ranging from 0.5 to 2.5 W/mK, resulting in high interface thermal resistance. Using low-temperature or eutectic solder, or hybrid solder pastes containing nanoparticles as thermal interface materials, can significantly reduce interface thermal resistance.
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